The present invention generally pertains to data processing systems, and is particularly directed to an improved synchronous priority circuit. A synchronous priority circuit, essentially includes "n" input terminals having a descending order of priority 1, . . . k, . . . n, wherein "k" and "n" are positive integers greater than 1; "n" output terminals corresponding to the "n" input terminals; and a logic circuit connected to the "n" input terminals and the "n" output terminals for causing a logical "true" signal to be provided from any given output terminal in response to a logical "true" signal being provided at its corresponding input terminal when a logical "true" signal is not provided at any priority input terminal. Only a single output terminal may provide a logical "true" output signal at any one time. A truth table for a synchronous priority circuit follows:
______________________________________ INPUTS OUTPUTS 1 2 k n - 1 n 1 2 k n - 1 n ______________________________________ 1 x x x x 1 0 0 0 0 0 1 x x x 0 1 0 0 0 . . . . . . 0 0 1 x x 0 0 1 0 0 . . . . . . 0 0 0 1 x 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 ______________________________________ 0 = FALSE 1 = TRUE x = DON'T CARE
Prior art synchronous priority circuits with a large number of input terminals either require too much silicon area and two much power, or they are too slow for contemporary VLSI technology.